(1) Field of the Invention
This invention relates in general to semiconductor device processing, and more particularly to a method of fabricating a multilayer metallurgy/insulator structure of a very large scale integrated (VLSI) circuit.
(2) Description of the Prior Art
Degradation of polysilicon load resistance in a double polysilicon interconnection metallurgy system, particularly in fabricating double polysilicon 4 transistor static random access memory devices. The fabrication of such devices depend on the use of multilayer metallurgy systems which contain a sandwich insulation composite layer of silicon oxide, spin-on-glass and silicon oxide, and the process steps for forming such silicon layers that utilize plasma enhanced oxidation.
Spin-on-glass is a very desirable material to be used in such methods and resulting structures to overcome the irregularity or substantially nonplanar surfaces of the first level of metallurgy. This irregular or nonplanar surface problem causes loss of resolution in the lithographic masking processing. The problem increases with higher level of metallurgy.
These problems have been recognized in the prior art and attempts have been made to overcome these topographical problems principally in the one micron and above feature dimensions. These techniques can be generally grouped in categories of planarization either involving etchback or nonetchback techniques.
In the case of etchback processing, typically a coating is formed on top of the irregular surfaces by an means of spin-on-glass or thermoplastic deposition techniques which produces a planar surface. A plasma, reactive or chemical wet etching is used uniformly across the planar surface to remove the deposited layer and the tops of the irregular humps or the like to produce a planar surface at the desired depth.
In the early nonetchback processing, the usual technique was to heat the dielectric layer, which was typically glass until the flow of the glass reduced the irregularities.
More recently the nonetchback planarization using a spin-on-glass sandwich has found interest at the about one micron feature dimension integrated circuit processing. This technique is described in U.S. Pat. No. 5,003,062 to Daniel L. Yen and assigned to the same assignee of the present invention. In this patent a sandwich dielectric structure is formed and used in one micron or less processing of spin-on-glass sandwiched between two silicon oxide layers. The spin-on-glass layer functions as the means for planarizing the irregularities.
In the Yen U.S. Pat. No. 5,003,062, spin-on-glass that has been cured still remains in the final product. However, workers in the field such as A. Malazgirt et al U.S. Pat. No. 4,986,878 has found that spin-on-glass even after curing by conventional techniques causes reliability problems, such as the presence therein of mobile ions, e.g. sodium to the point that they use the spin-on-glass in an etchback process for planarization and then completely remove the remaining material. Then a conventional insulator is deposited.
In the paper entitled "FIELD INVERSION IN CMOS DOUBLE METAL CIRCUITS DUE TO CARBON BASED SOGS" by D. Pramanik et al, a further discussion of the reliability problems in the use of spin-on-glass (SOG) is considered. They conclude that the use of SOG must be heavily restricted to overcome field inversion, that is a positive charge build up between the SOG layer and the other dielectric layers. They state that SOG must be purely inorganic phosphosilicate glass, since organic based SOG emanates hydrogen. Further, the require that etchback be used to reduce the thickness of the SOG to the bare minimum in the final product. Still further, they require that the layer covering the SOG be formed of a material that does not liberate hydrogen, such as silicon dioxide. Normal processes for depositing silicon nitride or oxynitride do liberate hydrogen.
In the U.S. Pat. application Ser. No. 07/743,779 Aug. 12, 1991 by L. S. Tsai et al entitled "Method and Resulting Device for Field Inversion Free Multiple Layer Metallurgy VLSI Processing" it is proposed that the inversion problem can be overcome by the incorporation of a specific dielectric between the Via 1 dielectric layer and the spin-on-glass (SOG) layer. This is a successful technique.
In another U.S. Pat. application Ser. No. 07/825,371 dated Jan. 24, 1992 by K. M. Lin et al entitled "A Nitrogen Treatment to Prevent Field Device Leakage in VLSI Processing" it is proposed that the inversion problem can be overcome by use of a nitrogen treatment of the first silicon oxide layer. This has been successful.
Accordingly it is a principal object of the present invention to provide a novel process for eliminating or substantially eliminating degradation of polysilicon metallurgy used in semiconductor devices.
Another object of the present invention is to provide a novel process for dispelling positive electrical charges in the multilayer metallurgy structures of VLSI circuits that would otherwise degrade the electrical characteristics of such devices without changing the established processes.